1. Field of the Invention
This invention relates to phase-locked loops (PLLs) and more particularly to PLL architectures that can provide high performance with low power utilization.
2. Description of the Related Art
Phase-locked loops (PLLs) are common in modern electronic systems. A high-level block diagram of a typical prior art PLL 100 is shown in FIG. 1. A phase/frequency detector (PFD) 103 compares a feedback divided signal 104 from feedback divider 105 and a reference clock signal 107. The difference is used to control the voltage controlled oscillator (VCO) 108. The PLL typically multiplies the reference clock signal using the feedback divider circuit 105. The divide value of the feedback divider 105 determines the amount of multiplication. Some PLL architectures are fractional-N PLLs where the PLL output 109 is a non-integral multiple of the reference clock 107. One aspect of PLLs is that the feedback divider tends to consume significant power because it is high speed and complex, particularly in fractional-N architectures.
As power is an important factor in many electronic designs, it would be desirable to achieve power savings in PLLs.